Known switched mode voltage regulators (VRs) may use digital controllers to generate the required load voltage from the input line voltage. The digital controllers include an input sampler implemented as an Analog-to-Digital Converter (ADC), a digital control loop controller, and a digitally implemented Pulse Width Modulation (PWM) generator, for example, using a digitally controllable delay line. Disadvantageously, each VR instantiation may either require an independent controller each with associated area and power overhead or alternately a smaller number of interleaved controllers may be deployed. In interleaved controllers, a single controller cycles between two or more voltage domains with the disadvantage of increased power from the ‘N’ sampling and clocking operations, where ‘N’ is the number of interleaved VRs.
In advanced deep sub-micron technologies, the area associated with the digital controller may be small, however, since ADCs rely on analog circuits, which do not scale to Moore's Law, they disadvantageously lead to an increased area and hence cost overhead. The interleaving approach additionally can be problematic to implement on advanced deep sub-micron process nodes due to the routing congestion and impedances associated with interconnect between local power islands and the time interleaved ADC, which may lead to error in the monitored voltage.
So conventional multiple controller instantiations (i.e., ‘N’instantiations) may be burdened with the power and area associated with ‘N’ ADCs and controllers, all running at 8×VR switching frequency (which may be in excess of 1 GHz for advanced controllers) or with a smaller number of time interleaved ADCs and controllers running at greater than ‘M’ GHz, where ‘M’ is the number of interleaved controllers. For example, embedded VRs may desirably run at a clock rate greater than 100 MHz and the ADC, and hence controller, may desirably run at a minimum of 8 times the oversampling frequency leading to high ADC and controller clock frequencies. These high frequencies result in high dynamic power consumption.